How to Use Git with Vivado FPGA Tools
Xilinx provides the Vivado FPGA (and Vitis software) tools for developing VHDL and Verilog FPGA designs. But they really don’t provide good information on setting up your project to work with Source Code Control (SCC). If you look through the Xilinx support forums you can see this has been a problem for at least a decade. Users were left to find their own solutions. Files for SCC were scattered throughout the directory structure. Finally, in recent years (2020 versions and later) Xilinx has attempted to address the problem by placing the files that need to be controlled under the <project.name>.srcs…